rubund
test fails
When I run make test after install I get this error and I don't know what it means. I'm installing on a clean LXD container running ubuntu 18.04.
Test project /home/ubuntu/graywolf/build Start 1: install_in_tmp 1/6 Test #1: install_in_tmp ................... Passed 0.01 sec Start 2: map9v3 2/6 Test #2: map9v3 ........................... Passed 4.93 sec Start 3: map9v3-twsc 3/6 Test #3: map9v3-twsc ...................... Passed 4.78 sec Start 4: map9v3-mincut 4/6 Test #4: map9v3-mincut .................... Passed 0.02 sec Start 5: map9v3-twmc 5/6 Test #5: map9v3-twmc ......................***Failed 0.02 sec Start 6: map9v3_other_seed 6/6 Test #6: map9v3_other_seed ................ Passed 4.84 sec
83% tests passed, 1 tests failed out of 6
Total Test time (real) = 14.61 sec
The following tests FAILED: 5 - map9v3-twmc (Failed) Errors while running CTest Makefile:94: recipe for target 'test' failed make: *** [test] Error 8
Same here, on the latest master state 6c5e24f. Here is the output of CTEST_OUTPUT_ON_FAILURE=1 make test:
Running tests...
Test project /home/localadmin/graywolf/build
Start 1: install_in_tmp
1/6 Test #1: install_in_tmp ................... Passed 0.01 sec
Start 2: map9v3
2/6 Test #2: map9v3 ........................... Passed 4.28 sec
Start 3: map9v3-twsc
3/6 Test #3: map9v3-twsc ...................... Passed 4.25 sec
Start 4: map9v3-mincut
4/6 Test #4: map9v3-mincut .................... Passed 0.02 sec
Start 5: map9v3-twmc
5/6 Test #5: map9v3-twmc ......................***Failed 0.03 sec
sending incremental file list
map9v3/
map9v3/map9v3.cel
map9v3/map9v3.mcel
map9v3/map9v3.par
map9v3/map9v3.scel
map9v3/map9v3.stat
map9v3/expected/
map9v3/expected/map9v3.blk
map9v3/expected/map9v3.gen
map9v3/expected/map9v3.gsav
map9v3/expected/map9v3.mdat
map9v3/expected/map9v3.mgeo
map9v3/expected/map9v3.mpin
map9v3/expected/map9v3.mpth
map9v3/expected/map9v3.msav
map9v3/expected/map9v3.mver
map9v3/expected/map9v3.mvio
map9v3/expected/map9v3.scel
sent 578,478 bytes received 336 bytes 1,157,628.00 bytes/sec
total size is 577,273 speedup is 1.00
/tmp/tmp.4S7cfcIVjg/map9v3 ~/graywolf/build/tests
TimberWolfMC version:v2.2 date:Mon May 25 21:18:34 EDT 1992
Authors: Carl Sechen, Bill Swartz, Kai-Win Lee
Dahe Chen, and Jimmy Lam
Yale University
config version:v1.0 date:Mon May 25 20:57:18 EDT 1992
Row configuration program
Yale University
config switches:
Graphics mode off
config terminated normally with no errors and 0 warning[s]
TimberWolfMC terminated normally with no errors and 0 warning[s]
--- map9v3.mdat 2020-02-11 14:24:56.098404760 +1030
+++ expected/map9v3.mdat 2020-02-11 13:06:04.502115887 +1030
@@ -8,9 +8,9 @@
pad 2 name twpin_clock
corners 4
--440 0 -440 160 -240 160 -240 0
+-440 8280 -440 8440 -240 8440 -240 8280
orient 7
-pin name clock signal clock layer 1 -340 80
+pin name clock signal clock layer 1 -340 8360
pad 3 name twpin_reset
corners 4
@@ -230,6 +230,6 @@
pad 39 name twpin_sr<7>
corners 4
--440 160 -440 320 -240 320 -240 160
+-440 140 -440 300 -240 300 -240 140
orient 7
-pin name sr<7> signal sr<7> layer 1 -340 240
+pin name sr<7> signal sr<7> layer 1 -340 220
--- map9v3.mgeo 2020-02-11 14:24:56.098404760 +1030
+++ expected/map9v3.mgeo 2020-02-11 13:06:04.502115887 +1030
@@ -1,7 +1,7 @@
cell core
6 vertices 0 0 0 18478 18478 18478 18478 9239 27717 9239 27717 0
cell pad.macro.l
-4 vertices -440 0 -440 8220 -240 8220 -240 0
+4 vertices -440 140 -440 8440 -240 8440 -240 140
cell pad.macro.t
4 vertices 240 18400 240 18600 23760 18600 23760 18400
cell pad.macro.r
--- map9v3.mpin 2020-02-11 14:24:56.098404760 +1030
+++ expected/map9v3.mpin 2020-02-11 13:06:04.502115887 +1030
@@ -1,5 +1,5 @@
net sr<7>
-pin sr<7> x -240 y 240 cell 2 layer 1 PinOrEquiv 1
+pin sr<7> x -240 y 220 cell 2 layer 1 PinOrEquiv 1
pin pin1 x 0 y 220 cell 1 layer 0 PinOrEquiv 1
net sr<6>
@@ -147,6 +147,6 @@
pin pin37 x 0 y 8140 cell 1 layer 0 PinOrEquiv 1
net clock
-pin clock x -340 y 80 cell 2 layer 1 PinOrEquiv 1
+pin clock x -340 y 8360 cell 2 layer 1 PinOrEquiv 1
pin pin38 x 0 y 8360 cell 1 layer 0 PinOrEquiv 1
--- map9v3.mpth 2020-02-11 14:24:56.098404760 +1030
+++ expected/map9v3.mpth 2020-02-11 13:06:04.502115887 +1030
@@ -3,7 +3,7 @@
The nets:
##############################################
-net 1:sr<7> xspan:340 yspan:20 length:360 numpins:2
+net 1:sr<7> xspan:340 yspan:0 length:340 numpins:2
net 2:sr<6> xspan:340 yspan:0 length:340 numpins:2
net 3:sr<5> xspan:340 yspan:0 length:340 numpins:2
net 4:sr<4> xspan:340 yspan:0 length:340 numpins:2
@@ -40,4 +40,4 @@
net 35:N<1> xspan:340 yspan:0 length:340 numpins:2
net 36:N<0> xspan:340 yspan:0 length:340 numpins:2
net 37:start xspan:340 yspan:0 length:340 numpins:2
-net 38:clock xspan:340 yspan:8280 length:8620 numpins:2
+net 38:clock xspan:340 yspan:0 length:340 numpins:2
--- map9v3.scel 2020-02-11 14:24:56.098404760 +1030
+++ expected/map9v3.scel 2020-02-11 13:06:04.502115887 +1030
@@ -3997,9 +3997,9 @@
pad 2 name twpin_clock
corners 4
--440 0 -440 160 -240 160 -240 0
+-440 8280 -440 8440 -240 8440 -240 8280
orient 7
-pin name clock signal clock layer 1 -340 80
+pin name clock signal clock layer 1 -340 8360
pad 3 name twpin_reset
corners 4
@@ -4219,6 +4219,6 @@
pad 39 name twpin_sr<7>
corners 4
--440 160 -440 320 -240 320 -240 160
+-440 140 -440 300 -240 300 -240 140
orient 7
-pin name sr<7> signal sr<7> layer 1 -340 240
+pin name sr<7> signal sr<7> layer 1 -340 220
~/graywolf/build/tests
Start 6: map9v3_other_seed
6/6 Test #6: map9v3_other_seed ................ Passed 4.26 sec
83% tests passed, 1 tests failed out of 6
Total Test time (real) = 12.86 sec
The following tests FAILED:
5 - map9v3-twmc (Failed)
Errors while running CTest
Makefile:94: recipe for target 'test' failed
make: *** [test] Error 8
Same problem here. Did u find a solution?
Running tests... Test project /home/dpfeiffer/Documents/Qflow_5R/graywolf/build Start 1: install_in_tmp 1/6 Test #1: install_in_tmp ................... Passed 0.22 sec Start 2: map9v3 2/6 Test #2: map9v3 ........................... Passed 4.28 sec Start 3: map9v3-twsc 3/6 Test #3: map9v3-twsc ...................... Passed 4.16 sec Start 4: map9v3-mincut 4/6 Test #4: map9v3-mincut .................... Passed 0.10 sec Start 5: map9v3-twmc 5/6 Test #5: map9v3-twmc ......................***Failed 0.12 sec sending incremental file list map9v3/ map9v3/map9v3.cel map9v3/map9v3.mcel map9v3/map9v3.par map9v3/map9v3.scel map9v3/map9v3.stat map9v3/expected/ map9v3/expected/map9v3.blk map9v3/expected/map9v3.gen map9v3/expected/map9v3.gsav map9v3/expected/map9v3.mdat map9v3/expected/map9v3.mgeo map9v3/expected/map9v3.mpin map9v3/expected/map9v3.mpth map9v3/expected/map9v3.msav map9v3/expected/map9v3.mver map9v3/expected/map9v3.mvio map9v3/expected/map9v3.scel
sent 578,455 bytes received 336 bytes 1,157,582.00 bytes/sec total size is 577,273 speedup is 1.00 /tmp/tmp.yuvkG3ytPM/map9v3 ~/Documents/Qflow_5R/graywolf/build/tests
TimberWolfMC version:v2.2 date:Mon May 25 21:18:34 EDT 1992 Authors: Carl Sechen, Bill Swartz, Kai-Win Lee Dahe Chen, and Jimmy Lam Yale University
config version:v1.0 date:Mon May 25 20:57:18 EDT 1992 Row configuration program Yale University
config switches: Graphics mode off
config terminated normally with no errors and 0 warning[s]
TimberWolfMC terminated normally with no errors and 0 warning[s]
--- map9v3.mdat 2020-05-19 14:07:55.378196158 +0200 +++ expected/map9v3.mdat 2020-05-12 17:00:47.724968158 +0200 @@ -8,9 +8,9 @@
pad 2 name twpin_clock corners 4 --440 0 -440 160 -240 160 -240 0 +-440 8280 -440 8440 -240 8440 -240 8280 orient 7 -pin name clock signal clock layer 1 -340 80 +pin name clock signal clock layer 1 -340 8360
pad 3 name twpin_reset corners 4 @@ -230,6 +230,6 @@
pad 39 name twpin_sr<7> corners 4 --440 160 -440 320 -240 320 -240 160 +-440 140 -440 300 -240 300 -240 140 orient 7 -pin name sr<7> signal sr<7> layer 1 -340 240 +pin name sr<7> signal sr<7> layer 1 -340 220 --- map9v3.mgeo 2020-05-19 14:07:55.378196158 +0200 +++ expected/map9v3.mgeo 2020-05-12 17:00:47.728968197 +0200 @@ -1,7 +1,7 @@ cell core 6 vertices 0 0 0 18478 18478 18478 18478 9239 27717 9239 27717 0 cell pad.macro.l -4 vertices -440 0 -440 8220 -240 8220 -240 0 +4 vertices -440 140 -440 8440 -240 8440 -240 140 cell pad.macro.t 4 vertices 240 18400 240 18600 23760 18600 23760 18400 cell pad.macro.r --- map9v3.mpin 2020-05-19 14:07:55.378196158 +0200 +++ expected/map9v3.mpin 2020-05-12 17:00:47.728968197 +0200 @@ -1,5 +1,5 @@ net sr<7> -pin sr<7> x -240 y 240 cell 2 layer 1 PinOrEquiv 1 +pin sr<7> x -240 y 220 cell 2 layer 1 PinOrEquiv 1 pin pin1 x 0 y 220 cell 1 layer 0 PinOrEquiv 1
net sr<6> @@ -147,6 +147,6 @@ pin pin37 x 0 y 8140 cell 1 layer 0 PinOrEquiv 1
net clock -pin clock x -340 y 80 cell 2 layer 1 PinOrEquiv 1 +pin clock x -340 y 8360 cell 2 layer 1 PinOrEquiv 1 pin pin38 x 0 y 8360 cell 1 layer 0 PinOrEquiv 1
--- map9v3.mpth 2020-05-19 14:07:55.378196158 +0200 +++ expected/map9v3.mpth 2020-05-12 17:00:47.732968236 +0200 @@ -3,7 +3,7 @@
The nets: ############################################## -net 1:sr<7> xspan:340 yspan:20 length:360 numpins:2 +net 1:sr<7> xspan:340 yspan:0 length:340 numpins:2 net 2:sr<6> xspan:340 yspan:0 length:340 numpins:2 net 3:sr<5> xspan:340 yspan:0 length:340 numpins:2 net 4:sr<4> xspan:340 yspan:0 length:340 numpins:2 @@ -40,4 +40,4 @@ net 35:N<1> xspan:340 yspan:0 length:340 numpins:2 net 36:N<0> xspan:340 yspan:0 length:340 numpins:2 net 37:start xspan:340 yspan:0 length:340 numpins:2 -net 38:clock xspan:340 yspan:8280 length:8620 numpins:2 +net 38:clock xspan:340 yspan:0 length:340 numpins:2 --- map9v3.scel 2020-05-19 14:07:55.378196158 +0200 +++ expected/map9v3.scel 2020-05-12 17:00:47.752968431 +0200 @@ -3997,9 +3997,9 @@
pad 2 name twpin_clock corners 4 --440 0 -440 160 -240 160 -240 0 +-440 8280 -440 8440 -240 8440 -240 8280 orient 7 -pin name clock signal clock layer 1 -340 80 +pin name clock signal clock layer 1 -340 8360
pad 3 name twpin_reset corners 4 @@ -4219,6 +4219,6 @@
pad 39 name twpin_sr<7> corners 4 --440 160 -440 320 -240 320 -240 160 +-440 140 -440 300 -240 300 -240 140 orient 7 -pin name sr<7> signal sr<7> layer 1 -340 240 +pin name sr<7> signal sr<7> layer 1 -340 220 ~/Documents/Qflow_5R/graywolf/build/tests
Start 6: map9v3_other_seed
6/6 Test #6: map9v3_other_seed ................ Passed 4.26 sec
83% tests passed, 1 tests failed out of 6
Total Test time (real) = 13.20 sec
The following tests FAILED: 5 - map9v3-twmc (Failed) Errors while running CTest Makefile:94: recipe for target 'test' failed make: *** [test] Error 8
I am getting the same test failure. has anybody determined if this prevetns greywolf from functioning properly? and how to fix it ?
I too was getting the same error on Ubuntu 18.04.
But then I was told to use clang as the compiler instead of gcc. And it worked!
I did
mkdir build
cd build
cmake -DCMAKE_C_COMPILER=/usr/bin/clang -DCMAKE_CXX_COMPILER=/usr/bin/clang++ ..
make
make test
which gave
Test project /home/user/graywolf-0.1.6/build
Start 1: install_in_tmp
1/6 Test #1: install_in_tmp ................... Passed 0.05 sec
Start 2: map9v3
2/6 Test #2: map9v3 ........................... Passed 11.09 sec
Start 3: map9v3-twsc
3/6 Test #3: map9v3-twsc ...................... Passed 10.22 sec
Start 4: map9v3-mincut
4/6 Test #4: map9v3-mincut .................... Passed 0.06 sec
Start 5: map9v3-twmc
5/6 Test #5: map9v3-twmc ...................... Passed 0.05 sec
Start 6: map9v3_other_seed
6/6 Test #6: map9v3_other_seed ................ Passed 11.22 sec
100% tests passed, 0 tests failed out of 6
Total Test time (real) = 32.71 sec
Not sure why this so though.
I am on gcc 7.5.0 and clang 6.0.0
Maybe a newer version gcc could make it work.
