rizwan3d
Elaboration of Verilog Generation
Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this project.
Hey there! Thanks for checking out the project! Yes, the Verilog generation is on the to-do list. The idea is to extend the capabilities of the code generator to support generating Verilog code, making it more versatile for hardware description. Your expertise as a Verilog RTL developer would be a fantastic addition! If you have any ideas or specific features you'd like to see, feel free to share. Contributions are always welcome!
Great, thanks for the response!
What did you have in mind for the Verilog generation feature? I'm having trouble seeing the kind of functionality here, since Verilog is used to infer digital logic to synthesise actual circuits, what kind of circuits are we trying to describe here? As far as I understand it, SharpRISCV is essentially a browser-based RISCV emulator that can run assembly code and generate executables. So I'm not too sure how Verilog fits in here is my confusion
Generate a Verilog code to load instructions and data memory for an FPGA, similar to what we did with the hex file.
Ah got it, makes sense. This sounds like a useful feature, I'd imagine I'd start off with generating a 'generic' rom file directly from the C#, that is simply just the raw instructions in hex format, represented as an appropriately sized 2D array and then eventually add some parameterisation to map it into specific Xilinx/Altera(now known exclusively as Intel since the acquisition) IP blocks. There'll be a bit of glue logic to generate to handle whether the IP block is sync/async but that doesn't sound too hard.
Cool, I'll fork this repo and have a play around over the next few days and show you what I get 👍