Support RISC-V assembler pseudo-instructions

[dnpetrov-sc]

For a full list see, for example, https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf, pages 110 and 111.

Currently some RISC-V assembly pseudo-instructions appearing in assembly output are decompiled to __asm statements. E.g.:

void do_integer_add () {
    a2 = *(a1);
    a1 = a2 + 57;
    a2 += 31;
    if (a0 == 0) {
        goto label_0;
    }
    do {
        a3 = a1;
        a0 += -1;
        a1 += a2;
        __asm ("negw a1, a1");
        a2 = a3;
    } while (a0 != 0);
    a0 = a3 + a1;
    void (*0x156f6)() ();
label_0:
    a0 = a2 + a1;
    return use_int ();
}

I've encountered similar issue with seqz and snez, and suspect some other pseudo-instructions are unsupported as well.

[wargio]

the problem is the disassembler is outputting the instructions in an old format. i need to update the disassembler first and then rewrite some stuff on jsdec