riscv-tests
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riscv-software-src
Hi all, I am working on a RISC-V emulator and right now implementing a hypervisor extension. I am using tests from this repo to test my implementation, however I noticed...
I can't figure out what mechanism is used to select what test suite is actually compiled. Or, what toolchain is used. For instance I am using the `buildroot` toolchain. Additionally,...
Use the `cease` instruction for this. It's unfortunately non-standard, but it does exist in Rocket so it's not crazy to use it here.
Dear maintainers, As you may know, Control State Register (CSR) is removed from base instruction in RV32I and RV64I version 2.1. So, we should remove the use of CSR related...
When I run `spike pk rv64ui-p-add`, it reported ``` bbl loader couldn't open ELF program: rv64ui-p-add! ``` I can't make sense how to use the riscv-test.
This API was introduced by c9f43c165 "Test daisy chained homogeneous spike instances. (#334)" where multiple logs were needed. However, this API was not implemented for `VcsSim` so verilated rocket chip...
The rv64ui-ma_data-v test runs indefinitely when run on spike for the `rv64imacsu` configuration. I have attached the log file and disassembly below. Looks like the `sp` is not being set...
`disassemble` shows the whole function which is usually too much. Instead just show the nearest instructions for some context.
When trying to compile riscv-tests with clang, several incompatible compilation issues between clang and gcc are met, such as: - https://github.com/riscv-software-src/riscv-tests/pull/225 - clang doesn't support immediates like `0f:7fc00000` - clang...
I run it with the command `spike pk benchmarks/dhrystone.riscv` ```bash $ spike pk benchmarks/dhrystone.riscv bbl loader couldn't open ELF program: benchmarks/dhrystone.riscv! ``` I checked the compile command. (riscv64-unknown-elf-gcc v10.2.0) ```bash...
