RISCOF needs to prevent fence.i in riscv-arch-test when not present in the ISA

[gsmecher]

On RV32IC architectures, the SAIL model currently fails with the following messages:

/path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S: Assembler messages:
/path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S:26: Error: unrecognized opcode `fence.i', extension `zifencei' required
/path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S:43: Error: unrecognized opcode `fence.i', extension `zifencei' required
/path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S:43: Error: unrecognized opcode `fence.i', extension `zifencei' required
riscv32-corev-elf-objdump: 'ref.elf': No such file

The first of these errors comes from the RVTEST_TRAP_PROLOG macro, defined in riscv-arch-test/riscv-test-suite/env/arch_test.h. Here, we have the following:

RVMODEL_FENCEI // make sure ifetches get new code

which is defined as follows:

#ifndef   RVMODEL_FENCEI
  #define RVMODEL_FENCEI fence.i                                // make sure ifetches get new code
#endif

It appears this macro is intended to be redefined when fence.i is inappropriate (e.g. when not implemented). RISCOF manages these macro definitions when SAIL test cases are compiled. However, it doesn't currently manage this one.

[gsmecher]

Similarly, if the ISA does include fencei ("ISA: RV32ICZifencei" in the ISA yaml), the appropriate "-mabi" string to enable fencei is not propagated to SAIL test cases and the same error occurs.

Unless I'm missing something, there's no way the current head-of-tree for RISCOF can work with the current head-of-tree for riscv-arch-test. (edit: it requires a recent compiler build, too; I think treatment of the -march string has recently gotten a lot stricter.)