riscof
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riscv-software-src
I get this message in several situations where IMO my ISA string should be accepted. Some examples: RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zkn_Zks_Zkt_Xfoo (Xfoo not recognized) RV32IMCNZicsr_Zifencei (says U must be with N, RV32IMCNUZicsr_Zifencei is...
Hi! Can you confirm if you have tested the test bclr-01.S (https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv32i_m/B/src/bclr-01.S) with Sail 0.5 as reference model? When I try to run it, the test runs indefinetly showing the...
this PR will add support for Zicbo* extension. It also add BLOCKSZ macro which will be used by tests for cbo.zero. The cache block size can be configured by riscv-config...
https://github.com/riscv-software-src/riscof/blob/b86c5079e4f46ca53258cf2cf438b5308f534cb7/riscof/Templates/setup/model/riscof_model.py#L183 This place (and some more) calls raise that calls exit. Exit exits before raise raises. This is very strange construction to me, especially raise on success. What are intentions...
https://github.com/riscv-software-src/riscof/blob/66bb6c468afaa3775ab5a757459a560ceaa5ee8c/riscof/Templates/setup/sail_cSim/riscof_sail_cSim.py#L116 Currently there isn't any support in riscof to feed in the flen to isac. Something similar as below would fix the issue. ``` coverage_cmd = 'riscv_isac --verbose info coverage...
I fixed a typo in a CLI and added a cosmetic update to a sentance.
It would be helpful to add the timeout option to section 4.7. I couldn't find it elsewhere in the docs, and I was getting a timeout error compiling on a...
