coreir

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Add with carry operator: `a + b + 1`

jeffsetter

``` /Users/ross/dev/coreir/build/tests/gtest/googletest-src/googletest/src/gtest.cc:4082:33: error: implicit conversion changes signedness: 'const char' to 'unsigned char' [-Werror,-Wsign-conversion] if (IsValidXmlCharacter(ch)) { ~~~~~~~~~~~~~~~~~~~ ^~ /Users/ross/dev/coreir/build/tests/gtest/googletest-src/googletest/src/gtest.cc:4083:56: error: implicit conversion changes signedness: 'const char' to 'unsigned char' [-Werror,-Wsign-conversion]...

rdaly525

Fixes #941

rdaly525

rdaly525

Add a Custom Name for CoreIR Generator When Generate Verilog

14

I am using coreIR to generate a memory placeholder in RTL for further power analysis. I want the RTL module which coreIR generator generated have the specific name matching with...

joyliu37

Request for CoreIR compatible with Windows.

1

If possible, could you implement CoreIR for Windows please? It could remove the hassle of using a VM.

Arka2BR

add verilog customized name for generator

2

I made some changes to the verilog analysis passes and it work for me for the issue. https://github.com/rdaly525/coreir/issues/941

joyliu37

Compilation error on Apple M1 chip

11

Hi all, Does anyone know how can I solve the errors in this compilation? Thanks a lot in advance I quote, "/Users/fengshi/Workspace/coreir/src/../include/coreir/ir/json.h:1636:11: **error**: '**construct**' is deprecated [-Werror,-Wdeprecated-declarations] alloc.construct(object.get(), std::forward(args)...); ^"...

shi27feng

See https://github.com/phanrahan/magma/pull/948/files/2d7143d433996917869a357bab0191ad4ba38ef7#r612759148

rsetaluri

For example, if i00.in0 is 16 bits, and I change this: ["self.in.0","i00.in0"] to this: ["self.in.0","i00.in0.0:16"] The add_dummy_inputs pass will wire a constant to every bit of i00.in0. Failing input file:...

jack-melchert