morty
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pulp-platform
A SystemVerilog source file pickler.
Hello, morty version 0.9.0 fails with a parse error in the following code example: ``` // filename: inside_test.sv module test (bit clk); int a,b,c; bit d; if (a inside {b,...
Add `.*` replacement capabilities as described in: **23.3.2.4 Connecting module instances using wildcard named port connections ( .*)** IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012) IEEE Standard for SystemVerilog
Hi there! Me again :innocent: Morty stack overflows on some CPU code. ## Output ``` thread '' has overflowed its stack fatal runtime error: stack overflow [1] 30715 IOT instruction...
If the source files contain multiple declarations of modules with the same name, the module graph will be built in a strange way. This should only impact the `graph_file` output...
Is it possible to add support for in-order/global defines? #mydefines.sv: ```` // This would take presedence until undef, or new value defined `define DW=32 ```` #mymodule.sv ```` // Define from...
Not directly related, but all those `
We are currently using `signal` as prefix in the ID of all `VarItems`. I wonder if we should change that to `var` to be closer to the language. _Originally posted...
Ideally, when able to also process comments, we can automatically parse documentation. Let's start by gathering some ideas here: - Document module hierarchy - ~Markdown comments at top of file,...
`sv-parser` gobbles comments after String literals into its whitespace vector. Consequently, they are not stripped from the sources. A minimal example: ```verilog // General comment module comment_module #( parameter blub...