common_cells
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pulp-platform
Common SystemVerilog components
The ‘sel’ signal currently acts (inverted) like the ‘drop’ signal seen in the likes of ‘stream_filter’. This may be intended behaviour but strikes me as somewhat unexpected. In my specific...
I wrote this assertion and it is failing. ``` generate for (genvar inp = 0; inp < NumInp ; inp++ ) assrt8_flush_with_ready_0: // when flush_i is asserted ready_o should be...
I am currently working on the formal verification of the stream_xbar. During my analysis, I have identified an abnormality in its behavior. In the 2nd clock cycle of the picture...
Several IPs internally instantiate a more generic version, leaving unneeded ports tied or unconnected. To ensure that only the required logic is instantiated, cross-boundary optimisations and constant propagation are needed,...
When downstream has backpressure, the flush function cannot work properly. so can we add the following sva property? assupe property ( @(posedge clk_i) disable iff (!rst_ni) flush_i |-> ready_i )...
in lzc module the comment says: /// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains /// the maximum number of zeros - 1. if...
Hi I am a french intern in computer architecture at Université paris saclay and I work on the implementation of IBEX in a low power system. I just started system...
For example: We can set up an always block generating a new clk_o based on whether the counter is gated or a new value is requested. Then we can do...
