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pulp-platform
RISC-V fast interrupt controller
Currently, we are forcing a 256 bytes alignment on `xtvec`.
This commit aims at resolving the critical path that originates in the CLIC target. Such critical path was detected in Carfield and Astral. This mod was tested working in [Carfield's...
Hi, I am linting the `clic_apb` module with Verilator using `verilator --lint-only --top-module clic_apb $(bender script verilator)`. There are a few warnings, but no errors. However, when I change the...
Extend CLIC to support interrupt delegation to virtual machines. Enabled / disabled by VSCLIC and VSPRIO parameters.
In CLINT mode, are reserved for special interrupt sources like software and timer interrupts. CLIC specification has this section: https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc#clic-interrupt-id-ordering-recommendations Does it make sense to prepare the IP for those...
clicintattr.trig allows run-time configurability of edge vs level and active high vs low. CLIC states: > Some implementations may want to save these bits so only certain trigger types are...
Most interrupt lists have gaps. Usually because a chip is available in many configuration with different peripherals. Sometimes sources are reserved to ensure you can grow in the future without...
I do not see a top level parameter to specify the number of interrupt levels. This would be important, as most designs will only need a few, not 256. I...
There have been quite some changes https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc. It would be good to review and implement these.