carfield
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pulp-platform
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
Changes: * Re-wired properly the JTAG chain on island disable * Added the safety + spatz config * Corrected pulp cluster CDC constraints * Modified device tree structure to have...
Fixing critical path in CLIC. Needs [#17](https://github.com/pulp-platform/clic/pull/17) before merging.
* Careful when routing the watchdog timer reset as it is a vital signal * Better to keep the watchdog disabled by default and then enable it
* Currently, a (largely) unoptimized flow involves the host to load a binary for a domain into shared SPM or the domain private SPM * Accelerate this flow with the...
@CyrilKoe you can refer to this issue when opening the PR addressing this part of the documentation
After #245 , the documentaiton will be missing some information. @yvantor I will do it ASAP, maybe next week. Opening this issue to make the misalignment evident to everybody
* Use https://github.com/pulp-platform/axi/tree/axi_lite_dw_converter/src, wait until it is merged into main in `axi`
A unaligned read from CVA6 to any address should result in an load exception. Currently, a double word load to `CAR_SAFETY_ISLAND_SPM_BASE_ADDR + 1` causes the core to lock up.
* Use `weak` attribute in `clk_init` function declaration to allow overwrites from external repositories using carfield as a dependency (e.g., a chip-specific repository) * Fix override of `CAR_SW_LIBS`
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A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.