axi_spi_master
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During a burst operation the data corresponding to higher address is returned first and then the data for lower address. See attached waveform 
Support for phase and polarity switching would be greatly appreciated. Is there any reason to not make these modes configurable?
s_eot signal not asserted for spi transactions without any data. E.g. NOR flash write enable, write disable commands. Thus programs using IRQ will lost such event interrupts.
spk_clk_div = 0 is generating spi clk @half clk frequency, and sdo missed first spi_clk rising edge thus first bit(s) was not latched correctly by slave. Delay en by 1...