Unsupported indexed segment ld/st instruction

[Fog-cake]

Hi, I found that arithmetic instructions often use m1 instead of m2 and m4 for testing. Does it not support multi register operation at present? And I haven't found the vector indexed and segment instructions yet. Is there anything I missed? such as： VSET(16, e8, m1); VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); asm volatile("vadd.vv v3, v1, v2"); VCMP_U8(1, v3, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);

I saw lmul = 2 except in the vlse64 instruction. But I don't seem to see where the hardware implementation is.

Thank you in advance.

[mp-17]

Hi Fog-cake,

Thanks for the question! LMUL != 1 should be supported by all the instructions, and the indexed memory operations are now being merged into the main branch with this PR https://github.com/pulp-platform/ara/pull/92. Segment memory operations are not currently supported, instead, as they became mandatory only in the last iteration of the specs. The natural addressing scheme should allow fetching the next elements in the subsequent registers when LMUL > 1. The checks for legal LMULs are in the Ara dispatcher. Let us know if you find something that does not make sense. In general, we will extend our verification strategy to verify more and more combinations of settings and instructions.

Best, Matteo