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Test different Ara parameters and instruction combinations
One of the ways in which Ara is currently verified is by running rv64uv tests following the riscv-tests approach (https://github.com/riscv/riscv-tests), i.e., verifying each instruction with ad-hoc tests exploiting common macros.
The riscv-tests are just a primer and do not exhaustively verify the design functionality under different combinations of parameters (vl, vstart, ...) and instruction intermixes. This should be addressed with specific tests.
Can you put the addition of extra kernels as another issue?