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Maybe Wrong AXI ID Width in Module ara_soc ?
Following axi id types exist in file ara_soc.sv:
localparam type axi_id_t = logic [AxiIdWidth-1:0]
localparam NrAXIMasters = 1;
localparam AxiSocIdWidth = AxiIdWidth - $clog2(NrAXIMasters);
localparam AxiCoreIdWidth = AxiSocIdWidth - 1;
typedef logic [AxiSocIdWidth-1:0] axi_soc_id_t;
`AXI_TYPEDEF_ALL(system, axi_addr_t, axi_id_t, axi_data_t, axi_strb_t, axi_user_t)
`AXI_TYPEDEF_ALL(soc_wide, axi_addr_t, axi_soc_id_t, axi_data_t, axi_strb_t, axi_user_t)
Above definitions are used to instantiate an axi crossbar in ara_soc.sv.
system_req_t system_axi_req;
system_resp_t system_axi_resp;
soc_wide_req_t [NrAXISlaves-1:0] periph_wide_axi_req;
soc_wide_resp_t [NrAXISlaves-1:0] periph_wide_axi_resp;
axi_xbar #(
.Cfg (XBarCfg ),
.slv_aw_chan_t(system_aw_chan_t ),
.mst_aw_chan_t(soc_wide_aw_chan_t ),
.w_chan_t (system_w_chan_t ),
.slv_b_chan_t (system_b_chan_t ),
.mst_b_chan_t (soc_wide_b_chan_t ),
.slv_ar_chan_t(system_ar_chan_t ),
.mst_ar_chan_t(soc_wide_ar_chan_t ),
.slv_r_chan_t (system_r_chan_t ),
.mst_r_chan_t (soc_wide_r_chan_t ),
.slv_req_t (system_req_t ),
.slv_resp_t (system_resp_t ),
.mst_req_t (soc_wide_req_t ),
.mst_resp_t (soc_wide_resp_t ),
.rule_t (axi_pkg::xbar_rule_64_t)
) i_soc_xbar (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.test_i (1'b0 ),
.slv_ports_req_i (system_axi_req ),
.slv_ports_resp_o (system_axi_resp ),
.mst_ports_req_o (periph_wide_axi_req ),
.mst_ports_resp_i (periph_wide_axi_resp),
.addr_map_i (routing_rules ),
.en_default_mst_port_i('0 ),
.default_mst_port_i ('0 )
);
This is where is I'm confused. In my understanding of axi crossbar, master ports of crossbar should has more id bits for identifying which master device has started this axi transaction. So should master ports of crossbar use type system_req_t instead for wider id width?