Prithayan Barua

[FIRRTL] Preserve 1D vector from MemToRegOfVec

3

Add an attribute `preserve_type` to preserve the 1D register generated from `MemToRegOfVec`.

Update the object model generated by the CreateSiFiveMetadata pass to generate `firrtl` dialect, instead of `om` dialect. Ensure all `firrtl.class` associated with the metadata are instantiated inside a top level...

The PR implements a new heuristic to determine if a Mux is reachable from a FirReg. In general an operation is reachable from a register if its in the fanout...

[LinkModules] Add support to link hw modules

4

Objective: Ensure that the HW modules preserve the hierarchical structure after linking. This is required to generate metadata from the final mlir, because only the om classes are not enough....

[FirRegLowering] Reimplement forward slice analysis with SCC

4

Implement an iterative SCC analysis to compute the forward slice analysis of `FirRegOp`.

Replace waiver comments with a new waiver attribute

1

Add a new attribute that can be used to emit X assignment waivers for memory. The attribute can be extended to handle other waivers, but currently only supports X-assignment. The...

This commit updates the heuristic to infer the enable signal drivers. Since temporary wires can be introduced by circt passes, the immediate `getConnectSrc` is not enough to infer the enable...

Handle the `RWProbeOp` in `CheckCombLoop`. This fixes https://github.com/llvm/circt/issues/6820

CombDataflow op interface should not exist in the HW dialect

1

The CombDataflow op interface is being used only in the FIRRTL dialect, `CheckCombLoops` pass, resolve the downstream dependencies to ensure the interface can be defined in the FIRRTL dialect. Related...

[Seq] Add a new op interface for clock transformation ops. NFC

1

Add the clock gate, clock inverter and clock divider ops to a new clock transformation interface. This makes it easier to handle them and get the input clock directly.