Prithayan Barua

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Thanks everyone for the initial feedback, this is ready for another iteration, please take a look.

> @prithayan is sim.printf used internally? @darthscsi , We don't use the `verif.print` op internally. The format string type looks good, would be useful for the `sim.plusargs` also.

> Does `ClockMuxOp` need to have this interface? In that case `getClk` returning a single value seems not composable. Yeah, I was not sure about clock mux, for the use...

Closing, as this can be accomplished via a simple function, the itnerface is not relevant.

Thanks a lot @fabianschuiki and @uenoku for the feedback. The major issue in the previous iteration was multiple instances. I have handled that in this version. The other concern regarding...

> @prithayan How breaking to you is this? Wire and connect is primarily being used with `libdn.channel` types, the wire serves a temporary, to use a value that is defined...