[FPGA] Add support for the FPGA simulator

[intel-jisheng1]

Add support for the FPGA simulator to run the code samples for max_interleaving, loop_ivdep, loop_unroll

Uses ext::intel::fpga_simulator_selector class to choose the simulator.

Existing Sample Changes

DirectProgramming/DPC++FPGA/Tutorials/Features/max_interleaving/ DirectProgramming/DPC++FPGA/Tutorials/Features/loop_ivdep/ DirectProgramming/DPC++FPGA/Tutorials/Features/loop_unroll/

Description

Add support for running these code samples on the FPGA simulator. Reduced data sizes to ensure reasonable execution times, as the simulator is 1000-10000x slower than the hardware

Type of change

• [X] New feature (non-breaking change which adds functionality)

How Has This Been Tested?

This has been run manually on Linux. Windows testing is on going.

• [X] Command Line
• [ ] oneapi-cli
• [ ] Visual Studio
• [ ] Eclipse IDE
• [ ] VSCode
• [X] When compiling the compliler flag "-Wall -Wformat-security -Werror=format-security" was used