PyLTSpice
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add_parameters and add_instructions to wrong places
Hi Thank you for this wonderful tool. But I encounter a problem when using together with the LTspicePowerSim.
E.g., when working with the VCO or idea diode model from this LTspicePowerSim, the instructions and parameters are added on their subcircuit, instead of top level. And then aborted the simulations. Example below:
.model D D
.lib C:\Users\tianxiao.chen\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m
K Lp Ls 1
.ic V(out)=12
.ic V(sw1,Vcr)={Vin/2}
.ic V(in,sw3)={Vin/2}
.ic V(sw3,hvgnd)={Vin/2}
.lib UniversalOpAmp2.lib
.PARAM Vin=48 ; Batch instruction
.PARAM R_pri=2m ; Batch instruction
.ic V(out)= 0
.backanno
.end
The batch instruction is placed inside the model D.
Or another exmaple inside .subckt VCO
.subckt VCO freq clk
C1 a 0 1
R1 b 0 1k
V2 N001 0 1
B2 a 0 I=IF(V(b),V(freq),0)
B1 N001 a I=IF(V(b),0,V(freq))
A1 b 0 0 0 0 0 clk 0 BUF
.machine
.state LO 0
.state HI 1
.rule LO HI V(a)>0.75
.rule HI LO V(a)<0.25
.output (b) state
.endmachine
.PARAM Vin=48 ; Batch instruction
.PARAM R_pri=2m ; Batch instruction
.ic V(a)=0.25
.tran 1m
.ic V(out)= 0
.ends VCO
Those are the last circuit/device in the netlist. Any idea how to solve? Thank you!!