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Cycle accurate Yamaha YM2151 emulator

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I don't know if this is a bug or not, but simple left or right panning produces fairly noticeable noise that isn't heard when centered.

After implementing the DT1 circuit following your code, I got several complaints about music being off-pitch. I have run your code to extract the same detune table as present in...

Comparing with the application notes, PMS results are reasonably close for all settings except PMS=7. For PMS=7 it should be 700 and the result is almost 800. ``` LFO (note)...

Values for DT2 frequency offset fade away for octave 7: ``` Oct Note | DT2=0 | DT2=1 | DT2=2 | DT2=3 -----------------|-------|-------|-------|------ 7 0 (2217 Hz) | 1.000 | 1.414...

I am changing my LFO implementation to fit the original architecture following your C translation of the chip. I have found a difference between my Verilog implementation (of your code)...

It looks like the envelope gets serial data starts showing at chip cycle 5, but the noise channel is latched at cycle 12. After cycle 12, the EG serial bit...

It seems that variables in the opm_t structure are registers in the original design, but some of them are not. One such example is _lfo_out2_b_. This variable is stored in...

The suffix __lock_ for signals latched for a clock cycle, for instance [here](https://github.com/nukeykt/Nuked-OPM/blob/cc63f6fa962ec30f937cb95a47345d43c4720b04/opm.c#L1596). Lock suggests that the signal will lock something else, whereas what happens here is that the signal...