nblei

https://github.com/TerosTechnology/vscode-terosHDL Also, I think it may be useful to look at TerosHDL to both distinguish Veryl from it, and also perhaps incorporate some if its ideas.

I think there's a very powerful idea here, Naoya. Rather than writing synthesis scripts in some typeless scripting language which has no understanding of the Verilog modules being synthesized, doesn't...

This is a nice idea. I think veryl should also support iterators (and type inference), so in addition to what you have listed: ```veryl always_comb { for (aa, bb) in...

A couple of things. Perhaps checker functions should be made by default, or with some type of pragma: ```rust #[derive(EnumCheckers)] enum foo_bar : logic { FOO, BAR } ``` Also,...

@saturn77 I like your suggestions for _non-tagged_ unions. I would suggest changing `#[derive(one_hot)]` to `#[encoding(one_hot0)]` to keep in line with SV (`$onehot` vs `$onehot0`). I would also suggest `one_cold` and...

@taichi-ishitani I really like your idea for creating class member functions for enums / user defined data types. Only thing I would suggest is that we do not introduce new...

I like this idea, and I think it fits more broadly into a discussion on what metadesign support should Veryl provide.

SV tasks which do not consume time are semantically equivalent to void functions.

Why should `logic` be invalid? Any variable or port of type `logic` can be elided when transpiling to SV.

Another note: Currently, veryl allows declaration of variably *lengthed* logic vectors: ``` module foo { var a: u32; var _b: logic; } ``` produces ``` module veryl_testcase_foo; int unsigned a...