microsoft
[Feature Request] Add RISC-V architecture support -- SHL EP
Describe the feature request
Currently, the RISC-V architecture is experiencing rapid development, and chip shipments are increasing day by day. Adding support for a RISC-V backend to ORT would be a great way to support AI model applications on RISC-V. In this Feature Request, we propose adding an SHL EP to ORT to enable support for RISC-V.
SHL(Structure of Heterogeneous Library, Chinese name: ShiHulan) is a high-performance Heterogeneous computing library for RISC-V CPUs with vector extension provided by T-HEAD. It is compatible with RISC-V v0.7.1 and v1.0 vector extension instruction standards.
Features for SHL: Reference implementation of c code version Assembly optimization implementation for XuanTie CPU Supports symmetric quantization and asymmetric quantization Support 8bit, 16bit, and f16 data types compaatible with NCHW and NHWC formates Use HHB to automatically call API Covers different architectures, such as CPU and NPU Reference heterogeneous schedule implementation
Describe scenario use case
Efficient AI inference for applications using ORT on RISC-V CPU
I have prepared some implementations, examples, and related tests, but I have some questions about CI I'd like to discuss with everyone. How to test this part of the content: We may need a RISC-V docker to test the related content, but how to add this part in CI, I am not sure how to proceed?
I am also currently engaged in RISC-V related work. I'm looking forward to this PR!
