Write a sequential circuit with register outputs.

[Nozidoali]

Describe the bug A register output (RO) created before a primary output (PO) will become a PO when writing to the BLIF file. (because write_blif always assume the first num_co index are POs and the rest are ROs).

To Reproduce

  sequential<klut_network> klut;

  const auto a = klut.create_pi();
  const auto b = klut.create_pi();
  const auto f1 = klut.create_or( a, b );

  klut.create_ri( f1 );
  const auto f2 = klut.create_ro(); // always_ff: f2 <= f1;

  klut.create_po( f2 );

  write_blif( klut, "<filename>.blif" );

Environment

• OS: Linux
• Compiler: GCC 12
• Compilation mode: DEBUG and RELEASE

Additional context In the current version (commit 39fd19c3215da2d395c769cfa92df578847ae6f7), ROs and POs are mixed in all network implementations.

Check list

• [x] I have tried to run in DEBUG mode and there was no assertion failure (or the reported bug is an assertion failure).
• [x] I have made sure that the provided code compiles and the testcase reproduces the error.
• [x] I have minimized the testcase.