[dv,top_earlgrey] Add some top earlgrey env features for use in future tests
Review commit-by-commit, these additions are all currently unused and should not affect existing tests.
I've just started reading through the commits one-by-one (and have only read the first one so far). I think I'm convinced that it's right, but it might make sense to expand the commit message to make it clear that the only code that consumes a sw_type_e is sw_symbol_backdoor_access, which basically just uses it as an index, so doesn't care if a new enum value gets added.
reviewed and all looks fine!
FPGA test failures are unrelated to this DV-only changeset
What is the reason for doing those changes in earlgrey_1.0.0 branch?
This PR (+ #28491 and #28194 , #28493) are in support of #28494, which allows for full simulation of the personalization provisioning stage. Setting up this simulation will be used to assist certain ATE bringup flows.
Does this conflict with other closed source DV changes?
What is the reason for doing those changes in earlgrey_1.0.0 branch?
This PR (+ #28491 and #28194 , #28493) are in support of #28494, which allows for full simulation of the personalization provisioning stage. Setting up this simulation will be used to assist certain ATE bringup flows.
Does this conflict with other closed source DV changes?
It is just that it is not relevant anymore for ealgrey_1.0.0 ATE so it is better to avoid any unneeded "noise" in this branch. Is it possible to merge it to master branch instead?