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[SPI,dv] Remove 30MHz SCK usage when not using two_stages_full_cycle …

Open sha-ron opened this issue 1 year ago • 1 comments

…read pipeline. SCK frequency bigger than 24MHz is supported only when CMD_INFO.read_pipeline_mode is set to 0x2. Currently the test is using CMD_INFO.read_pipeline_mode=0x0.

sha-ron avatar Sep 19 '24 09:09 sha-ron

Thank you for the review @rswarbrick. CMD_INFO (that includes read_pipeline_mode field) is actually a set of registers and the test has internal loop over a few commands so I am not sure how to find the correct read_pipeline_mode configuration. I opened https://github.com/lowRISC/opentitan/issues/24597 regarding missing configurations in SPI pass through mode. I guess that someone who knows better SPI will have to refactor this test anyway or create a new test for the missing configurations.

sha-ron avatar Sep 19 '24 15:09 sha-ron

Thanks @hcallahan-lowrisc for your review, and for looking into this together with @antmarzam . I'll now merge the PR and cherry-pick it over to earlgrey_1.0.0 together with some other changes.

Once the real solution is there, we can also merge and cherry-pick it over.

vogelpi avatar Oct 03 '24 08:10 vogelpi