[spi_host] Control of WP and HOLD for single- and dual-lane modes

[jesultra]

Description

The spi_host supports single, dual or quad mode transfers. When quad mode is achieved by using WP and HOLD signals for D2 and D3, and for such transactions, the SPI IP logic will drive all four Dx pins in step with the SPI clock.

When using single or dual mode, it seems that the SPI IP logic currently leaves WP and HOLD floating, which may be undesirable since that basically requires an external pullup on WP and HOLD, in case the OT chip wants to do some initial communication using single lane, (maybe in order to discover the capabilities of the SPI flash chip.)

I would like to request additional bits in a SPI host CONTROL register, for each of the WP and HOLD outputs, I would like to choose between three options: low, high, Hi-Z, which should apply to the respective outputs any time between SPI transactions, as well as during single and dual mode transactions, (subject to OUTPUT_EN).

[a-will]

Use the pinmux pad controls to set pull ups. See https://opentitan.org/book/hw/ip/pinmux/doc/registers.html#dio_pad_attr--pull_select

[jesultra]

You are right, we can probably live with built-in pullup (or pulldown), and do not require the ability to strongly drive the D2 and D3 pins while doing non-quad SPI.

[jesultra]

I believe that the ability to control weak pill from the pinmux will satisfy the needs of ChromeOS, since the SPI IP seems to always tri-state the D2 and D3 lines when doing single or dual mode communication.