[dv] Verify Lockstep checking

[GregAC]

Build a testbench component to corrupt outputs from both the lockstep and main cores and corrupt inputs into the lockstep core and ensure suitable alerts are triggered.

This will be complicated by the fact that corrupted outputs from the main core could result in co-sim mismatches. It may be necessary to disable co-sim checking around the corruption.

Note that not all corruptions of inputs would necessarily trigger a change of outputs. Interrupt corruption should be targeted to ensure it will result in a change of outputs.

A more complete test would also try corruptions of the internal signals of both cores. Again careful targeting will be required to ensure it will definitely cause a change in behaviour.

This testing is not intended to fully verify all possible scenarios where the lockstep comparison would catch a glitch but should aim to trial corruptions on all inputs and outputs.

estimate 32