lowRISC
Ibex does not reflect instruction memory changes to ICache
If ICache is enabled and a write to a cached instruction memory (which we are allowed to do) occurred, Ibex does not let ICache know such a store happened. As a result, cached instruction will not change inside ICache (but it will change in the memory component) and when PC will point to that address, Ibex will use the cached instruction. That causes mismatches between ISS and RTL.
It is probably not the most important corner case but I thought it might be good to document it as an issue for future.
It's acceptable for our icache to not be coherent so I'd wouldn't class this as an RTL bug, more a documentation issue.
Though we probably shouldn't be overwriting code in RISCV-DV generated programs.
