[dv, fcov] Debug related coverage holes

[GregAC]

@hcallahan-lowrisc assigned to all of these

The following debug related coverpoints are not yet being hit:

• [ ] Some categories for single stepping over each instruction category - cp_single_step_instr - Orig Estimate 4. Remain 2022-07-28 2. Remain 4 2022-08-01. Remain 4 2022-08-03. Remain 1 2022-08-10.
  • [ ] CSRAccess
  • [ ] EBreakDbg
  • [ ] EBreakExc
  • [ ] ECall
  • [ ] MRet
  • [ ] DRet - Illegal bin?
  • [ ] WFI
  • [ ] Fence
  • [ ] FenceI
  • [ ] FetchError
  • [ ] CompressedIllegal
  • [ ] UncompressedIllegal
  • [ ] CSRIllegal
  • [ ] PrivIllegal
• [ ] Hardware breakpoint triggered - cp_insn_trigger_enter_debug - Orig Estimate 8. Remain 2022-08-16 4. Remain 2022-08-26 1.
• [ ] Hardware breakpoint on instruction that causes an exception cp_insn_trigger_exception - Orig Estimate 8. Remain 2022-08-16 4. Remain 2022-08-26 1.

Note for some of the single step instruction categories it's possible we simply cannot trigger the coverpoint for those. However from an initial look I think it should be possible for all of them (other than None)

Original HW/PM estimate 20

estimate 30 remaining 2022-07-27 16 remaining 2022-08-01 18 remaining 2022-08-03 18 remaining 2022-08-10 15 remaining 2022-08-16 9 remaining 2022-08-23 5 remaining 2022-08-26 3

[hcallahan-lowrisc]

Update for 2022-07-27 : In progress for cp_single_step_instr 2 remaining Also now 6 remaining for cp_insn_trigger_enter_debug

[hcallahan-lowrisc]

Update for 2022-08-01 : In progress for cp_single_step_instr, increased remaining to 4, revised estimate up +6

[hcallahan-lowrisc]

Update for 2022-08-03 : In progress for cp_single_step_isntr, remaining still at 4, revised estimate up +4

[hcallahan-lowrisc]

Update for 2022-08-10 : In progress for cp_single_step_instr, remaining 1 PR out, still need to hit one cover-point, hopefully improvements to csr randomization in riscv-dv will make this easy.

[hcallahan-lowrisc]

Update for 2022-08-16 : In progress for cp_insn_trigger_* coverpoints, remaining 4 for each. I'm working on a new directed stream for riscv_dv which inserts a short sequence of instructions which enable the trigger and set the address to a randomly-generated insn at the end of the stream. With appropriate randomization this should allow us to hit both coverpoints.

[hcallahan-lowrisc]

Update for 2022-08-23 : In progress for cp_insn_trigger_* coverpoints, remaining 2 for each.

[hcallahan-lowrisc]

Update for 2022-08-26 : In progress for cp_insn_trigger_* coverpoints, remaining 1 for each. Just need to do a little tidyup and create some PR's.