[rtl] Check and fix IRQ entry latency for 2-stage config

[vogelpi]

In #1304 , we discussed that there might be an additional cycle of latency added when entering and interrupt handler in the 2-stage configuration. See https://github.com/lowRISC/ibex/pull/1304#discussion_r594375140 for more details.

We should check if this can be fixed easily.