About the constraints for tileable routing

[narutozxp]

Hello, I had read your paper, "A Study on Switch Block Patterns for Tileable FPGA Routing Architectures", which mentioned some constraints to tileable routing. First of all, $W = \Sigma f_L \cdot L$. However, such a constraint can't guarantee an even channel width. So should W be $\Sigma f_L \cdot 2L$? Second, the array size should be the multiple of all the lengths of wires, in order to guarantee regular wires even at the fringes of FPGAs. However, due to the twisted wire, there should be the same topology in all switch blocks, so, the array size seems don't matter.