[circt-verilog] 'moore.case_eq' operand must be simple bit vector type, but got array

[AtticusKuhn]

I ran circt-verilog on this file from OpenTitan: https://github.com/lowRISC/opentitan/blob/d8b5efd1427152b8387d6e03d9db413167e58475/hw/ip/lc_ctrl/rtl/lc_ctrl_fsm.sv

I got this error:

ak2518@autobot:/local/scratch/ak2518/opentitan$ /local/scratch/ak2518/circt/build/bin/circt-verilog --debug --parse-only /local/scratch/ak2518/opentitan/hw/ip/lc_ctrl/rtl/lc_ctrl_fsm.sv -yhw/ip/prim_generic/rtl -yhw/ip/prim/rtl -yhw/ip/lc_ctrl/rtl -yhw/ip/rom_ctrl/rtl -Ihw/ip/prim/rtl -yhw/ip/prim_generic/rtl -DYOSYS -DSYNTHESIS  --mlir-print-ir-after-failure --verbose-pass-executions --mlir-pass-statistics
Args: /local/scratch/ak2518/circt/build/bin/circt-verilog --debug --parse-only /local/scratch/ak2518/opentitan/hw/ip/lc_ctrl/rtl/lc_ctrl_fsm.sv -yhw/ip/prim_generic/rtl -yhw/ip/prim/rtl -yhw/ip/lc_ctrl/rtl -yhw/ip/rom_ctrl/rtl -Ihw/ip/prim/rtl -yhw/ip/prim_generic/rtl -DYOSYS -DSYNTHESIS --mlir-print-ir-after-failure --verbose-pass-executions --mlir-pass-statistics
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-:148:13: error: 'moore.case_eq' op operand #0 must be simple bit vector type, but got '!moore.array<6 x l5>'
-:148:13: note: see current operation: %243 = "moore.case_eq"(%239, %242) : (!moore.array<6 x l5>, !moore.l30) -> !moore.i1
ak2518@autobot:/local/scratch/ak2518/opentitan$

I'm not sure what this error means. I don't know how to debug/inspect the intermediate representation before the error happens. It would be useful if I could see what construct in the original SystemVerilog caused this line in the MLIR.

version:

ak2518@autobot:/local/scratch/ak2518/opentitan$  /local/scratch/ak2518/circt/build/bin/circt-verilog --version
LLVM (http://llvm.org/):
  LLVM version 22.0.0git
  DEBUG build with assertions.
CIRCT 55f12edd1
slang version 9.0.0+54385bb

Through trial-and-error, I've realised that this is caused by lines 148-203 in lc_ctrl_state_transition.sv https://github.com/lowRISC/opentitan/blob/d8b5efd1427152b8387d6e03d9db413167e58475/hw/ip/lc_ctrl/rtl/lc_ctrl_state_transition.sv#L148-L203

[fabianschuiki]

Excellent find! Pretty sure this is a case ... endcase statement with packed arrays either as the case expression, or the individual caes item expressions. I think all that's needed is for the case statement lowering in ImportVerilog/Statements.cpp to convert the case expression and each case item expression to simple bit vectors.