Cannot append System Verilog output tests to sv-dialect.mlir

[mikeurbach]

This is obviously not a huge deal, but there is a slight inconvenience in that it appears to be impossible to add new System Verilog tests at the end of the file. It looks like this is because the last tests in the file are checking labels in the MLIR output, which is emitted after all the System Verilog: https://github.com/llvm/circt/blob/a89324428efef0120337f7b0e7de1164f5775693/test/Conversion/ExportVerilog/sv-dialect.mlir#L1465-L1473

The rest of this file is checking System Verilog output, but the above makes adding new System Verilog checks at the end of the file impossible. @prithayan it looks like you added the above tests in https://github.com/llvm/circt/commit/333089b9b39137b98061b43a01d77496991633f9, is there any specific reason for them to be in that file, or could we move the MLIR checks elsewhere?