socitrack icon indicating copy to clipboard operation
socitrack copied to clipboard
verified publisher icon lab11

Rev O ToDos

Open ppannuto opened this issue 1 year ago • 2 comments

Not done from #58:

  • [ ] #56, or consider added dedicated connector
    • [x] Maybe: Restore optional USB footprint

DFM notes to revisit:

  • [ ] Much of the silkscreen is not printable.
    • The recommended line thickness for silkscreen is 6-mil (0.15mm).
    • Also, we recommend you avoid, as much as possible, any silkscreen on top of exposed copper. Highlighted are just a few examples. Any silkscreen left on top of exposed copper will be trimmed by our CAM team before the data is sent to the fab.
  • [ ] Remove silkscreen from nearby fine pitch components
    • We are finding that as components get smaller, the little bit of silkscreen near those components can actually create a small gap between the stencil and the pads. From our experience, eliminating this silkscreen has had a significant impact on our first pass yield.
    • We have all of the polarity information we need from your EDA upload anyway, so we wouldn't need the polarity indicators either.
    • Interestingly, I recently attended a conference and had lunch with a DFM engineer from a very large CM (top 10 in the world) and he told me that they're eliminating silkscreen entirely from all of their projects, except for part numbers and other aesthetic features.
    • We discussed stencil printing on episode 7 of our podcast
    • We discussed stencil design in a 2 part episode (ep 74 and ep 75)
  • [x] Trace width and gap and min hole (check for opportunities to improve this)
    • Your trace widths and gaps look good for 1oz copper, but it is on the very lowest end of most PCB fabs capabilities.
    • For higher yields and quicker turns, you may want to get to 5-mil gaps wherever possible.
    • The 4-mil drill is very small, but since your PCB is only 0.6mm thick it should be ok.

Manufacturing Notes:

  • [x] Part S4 (MM8030 RF bypass) missing solder paste (cream) cutout
  • [x] Apollo4 and 9DOF don't multiplex I2C/SPI wires in the same way:
    • The 9DOF has
      • I2C-SCL and SPI-SCLK shared
      • I2C-SDA and SPI-MISO shared
      • n/a, dedicated SPI-MOSI
      • image
    • But the Apollo4 does
      • I2C-SCL and SPI-SCLK shared [okay]
      • I2C-SDA and SPI-MOSI shared [different!!]
      • n/a, dedicated SPI-MISO
      • image

Board Testing Notes:

  • [x] The RED/YELLOW GPIO pins are switched (prob easiest to just change the labels in the schematic, doesn't affect anything)
  • [x] Ground plane near Qi switch not connected as well for no material reason (almost certainly non-issue, but easy fix):
    • image, image
  • [ ] Ask CH about glue option for speaker, switch?
    • image
  • [ ] Update TPs to use consistent part, put on dedicated test layer?
    • image
  • [ ] Similarly, update fiducial to be on dedicated reference layer?
    • image

ppannuto avatar Oct 21 '24 21:10 ppannuto

  • [x] R26 on revN is not properly grounded (the measured voltage at the GND end is ~0.6V, not 0), causing the output voltage of 2.5V rail to stay at Vref (~0.6V) due to circuitHUB gerber issues
  • [x] R13 on revN is not grounded, causing wireless charging to be not responsive
Image

corruptbear avatar Jan 15 '25 22:01 corruptbear

CHANGELOG

  • Remove RX14, connect R13 to GND
  • Explicit GND connection for R26
  • Rename USB parts as do-populate (XR16 -> R12; XR17 -> R13; XJ1 -> J7)
    • Also renumber some R's to fix order by value (R13->R10; R15->R11; R12->
  • Remove unused SWTRACE debug header to free up accessible GPIOs
    • Was GPIO38 -> SWTRACECLK and GPIO80–83 for trace data
  • Connect USB data to AP4
    • Add TVS diode to D+/D-
    • Add VR4 and VR5 to supply AP4 USB3.3 and USB0.9 respectively
      • Provide dedicated control to each EN pin on this rev; expect to tie these together in a future rev
      • Hang both VRs off VBAT_SWITCHED
      • GPIO78 <> Enable AP4 VUSB 0P9
      • GPIO81 <> Enable AP4 VUSB 3P3
    • Add VUSB cable detect
      • Implemented as resistor divider to reduce to AP4 I/O logic voltage (and act as pull-down when VUSB floats)
      • GPIO80 <> USB CABLE DETECT [high=cable present]
  • Replace RZ8 with SJ8 (AP4 MIPI Supply <> GND connection)
  • Remove S4, the UWB RF sample probe point
  • Move LNA (U7) to RF common path instead of just ANT1
  • Remove RX1; was dedicated hedge for LNA regulator control, wasn't used on Rev N, and the SJ4 hedge is still present for overriding DW_EXTON signal.
  • Replace RZ10 with wire; was hedge for VR2 (AP4 VDDAUDA) supply EN pin
  • Replace RZ11 with wire; was hedge for VR2 output (supply to AP4 VDDAUDA)
  • Upsize most of the 4mil vias north of AP4 to 8mil vias
  • Delete SJ1; was hedge for LED supply voltage connection, proven now.
  • Remove CX5; was DNP cap on BLE RF path in ref sch; we've never used.
  • Remove CX1, CX2; was optional caps for RF switch control; unlikely hedge from EVB schematic, unused in practice.
  • Remove RX8; was external pullup option for IMU !RESET line; never used.

Larger layout changes

  • Move UWB (U2 and support) up a bit to allow LNA (U7) to be inline with RFC path
  • Move regulator for LNA (VR3) into UWB block
    • Rationale: less zig-zag for VR3_OUT to new LNA location; also opens up space near power supply if needed
  • Explicit connection from every top metal GND pad to a via
    • Verified by visual inspection, as I don't think I can get Fusion to do this, and it's way too noisy (~300 airwires) to explicitly connect every GND signal on the board, mostly the vias
  • Try to get to 40 mil clearance from edge of board everywhere for manufacturability
    • Scrunch LEDs, buzzer, and support passives tighter.
    • Scrunch BLE RF passives down (space from removed CX5)

Component Renames

  • CX{3,4} -> CX{1,2}; DNP cap pads for AP4 32 MHz crystal
  • SJ2->SJ1, XR19 -> RX1; option to disable BQ24040 thermal protection
  • RX7 -> RX2; PRETERM adjustment option for BQ24040; never used, but in a sparse area of board and no harm in keeping
  • RX2 -> RX3; external pullup option for !CS for flash; keeping more as a test point pad than pullup option
  • RX{5,6} -> RX{4,5}; external pullup options for non-default I2C IMU connection; probably can delete the whole I2C option at some point...
  • SJ7 -> SJ4; PS1 pin of IMU, chooses I2C vs SPI (vs UART); similarly can delete in future
  • SJ4 -> SJ2; option to disable DW_EXTON control, which drives VDD2/3 power supplies for DW
  • SJ8 -> SJ7; AP4_VDDMIPI tie to GND; don't really need as hedge, but AP4 power stuff is so touchy that keeping the option feels good
  • RZ9 -> RZ6; AP4_VDDBH{_RF} supply; matches AP4 EVB hedge; never used..., but AP4 power still makes me nervous, so keeping for now
  • Ordering remaining R's by value / filling gaps:
    • R20->R14, R23->R17, R{24,25}->{19,20}, R26->R21, R27->R22, R{28,29}->R{24,25}, R30->R27, R{31,33,34}->{28,29,30}
    • BOM Reduction Analysis:
      • Could replace R19/20 (arbitrary 100k pulldowns) with existing value; probably 10k; defer for the moment as I don't have time to reason through DW3110 implications
      • Other values are largely application specific, or appropriate copies of app-specific √
  • Ordering/reducing caps will have to wait for another rev :/

Cosmetics

  • Up as much silk as was easy to 30 mil @ 20% (6 mil stroke)

Manufacturer Part No's

  • C{12,13,14}: KEMET renamed C0603C472J5GAC7867 --> C0603C472J5GACTU
  • C{38,39}: Arbitrary 0.47µF cap used for BQ51013B CLAMP, Murata discontinued their prior park; use a TDK replacement (C1005X5R1E474K050BB).
  • L6: Murata EOL'd DFE18SAN1R0ME0L. Their recommended replacement is a higher-current 0805. Replace instead with similar spec'd MCKK1608T1R0MN from Taiyo Yuden.
  • L4: Würth coil is out of stock everywhere; replace with WRSR-16R7K-11
    • note: this isn't updated in fusion source currently, just CH order b/c of library headache that I need to debug (missing ac library? old part..)

ppannuto avatar Jan 31 '25 22:01 ppannuto