riscv-vector-tests
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ksco
Unit tests generator for RVV 1.0
Thanks for the test suite. It's super helpful for developing simulators and RTL. Maybe I missed something but I think the tests currently don't take into accout `vxrm`, `frm`, `mstatus`,...
After meeting prerequisites, I execute `make -j40`. However, I got the error message as follows：  I check the related files and find that the function `cfg_t::cfg` is called in...
When VLEN=128, some Zvk tests are generated with fractional LMUL, which becomes an illegal instruction - for instance, with `vaesf1.vi`
Hello, I want to verify my riscv vector extension co-processor, but couldn't find the vector test suites in the riscv-arch-test repo. I just found this generator for vector tests, so...
I'm not very familiar with Go. Right now, I have a custom instruction and I want to use this project to automatically generate test cases for it. I know I...
RVVM uses a forked `riscv-test-env` tree where `write_tohost` is implemented via printing results to UART and shutting down the machine. This can be seen here: https://github.com/riscv/riscv-test-env/commit/002df18087a5f7c7d068757329244adde3243e93 This works well for...
When building executables with VLEN equal to 64, faulty patches are generated for at least one instruction. For XLEN=32: ``` build/merger -stage1output out/v64x32machine/tests/stage1/ -stage2output out/v64x32machine/tests/stage2/ -stage2patch out/v64x32machine/patches/stage2/ fatal: wrong patch...
Potential issue with test case for indexed-unordered segment stores due to variance in storage order
### Description: When testing the vsuxseg2ei16 instruction, the test case fails under specific conditions. Upon further analysis, it was found that address overlap in the test cases, according to the...
### Description: When testing the vssseg2e16 instruction, the test case fails under specific conditions. Upon further analysis, it was found that when the stride value is set to 2, according...