Support for Verilog 2001 attributes?

[mithro]

So I saw in #3 that you are looking at trying to keep hdlparse simple and targeted at just being used for documentation generation.

In the IEEE Verilog 1364-2001 standard, an attribute is a way to add information to a Verilog object, statement or groups of statements that is tool-specific and does not affect simulation of that design. All Verilog-2001 attributes begin with the token (* and end with the token *). An attribute can be multi-line and is "attached" to the Verilog object, statement, or group of statements that is specified immediately beneath the attribute.

An example of an attribute is shown below;

(* preserve *) reg my_reg;

I think these attributes would be super useful to be included in documentation. In fact, I think you could probably use attributes for the "symbol-sections" inside Symbolator.

From reading the following page it seems fairly standard to support using attributes or special comment forms for specifying this type of special information. See below;

To use a synthesis attribute or directive in a Verilog Design File you can use the (* and *) delimiters. For example, you can use the following code to use the preserve synthesis attribute:

(* preserve *) reg my_reg;

You can also use a synthesis attribute or directive if you specify the synthesis attribute or directive in a comment in the file. The comment can use one of the following formats:

/* <comment> */
// <comment>

For example, you can use the following comment to use the preserve synthesis attribute in a Verilog Design File:

reg my_reg /* synthesis preserve */;

To use more than one synthesis attribute and/or directive for a single node, separate the synthesis attributes and/or directives with a space. For example, you can use the following comment to use the maxfan and preserve synthesis attributes for a single node:

reg my_reg /* synthesis maxfan = 16 preserve */;

Looking at this page these attributes can also be useful for adding more information about things like finite state machines;

 (* covered_fsm, channel, is="state", os="next_state",
                           trans="STATE_IDLE->STATE_IDLE",
                           trans="STATE_IDLE->STATE_HEAD",
                           trans="STATE_HEAD->STATE_DATA",
                           trans="STATE_HEAD->STATE_TAIL",
                           trans="STATE_DATA->STATE_DATA",
                           trans="STATE_DATA->STATE_TAIL",
                           trans="STATE_TAIL->STATE_HEAD",
                           trans="STATE_TAIL->STATE_IDLE" *)
  always @(reset or state or head or tail or valid)
    ...

Would you accept a patch which adds support for these?

[tejaverilogattribute]

hi all, i'm trying to write the pin_numbers synthesis attribute

i tried like this: (* synthesis pin_numbers = "143" *) input in;

showing an error, can anyone help?