Kees Jongenburger

Under Linux the file names are case sensitive hence this error message was given: Field 'browser' doesn't contain a valid alias configuration 14 /home/keesj/projects/llm/writer/src/components/Header/Header doesn't exist

Reaload button not fully working

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The reload functionality on f11428052b3ca572957b4face9ba8c937d9408b4 (current head) is broken Steps to reproduce Given the following verilog code ``` `timescale 1ns/1ps `default_nettype none module clk_tb; reg clk =1'b0; always begin #5...

Ubuntu WSL2 Missing dragging handle bars

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I noticed that when running gtkwave under WSL2 most of the time I am missing the handle bars that allow to resize the panes. It is still possible to move...

I recently discovered fstminer and I like being able to search for a pattern in the fst file. This functionality would also be nice in gtkwave (search for pattern in...

zha got and unexpected keyword argument enable_mains_startup_polling

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### The problem I am runing home assistant (pip / venv) and upgraded to 2024.10.1 and I am getting the following error: ``` File "/home/home/home/lib/python3.12/site-packages/homeassistant/config_entries.py", line 594, in async_setup result...

``` keesj@Swift:~/tmp/verible$ verible-verilog-format --version v0.0-3890-g2585d6a3 Commit 2024-12-24 Built 2024-12-24T16:43:13Z ``` When I start my verilog file with two consecutive directives (the timescale and the default_nettype) the formatter puts them on...

I have verilog code that is included into a litex project and I want to be able to use this code in both simulation and for synthesis. This is currently...