Configuring VHDL Generator to use entity instantiation.

[andrewandrepowell]

Hello!

As the title states, is there a way to configure the VHDL Generator to generate VHDL with entity instantiations (e.g. ff_inst : entity ex_lib.ff(rtl)), instead of component instantiations (e.g. ff_inst : ff)?

[epekkar]

Hi Andrew,

Currently only component instantiations are created in VHDL generation. I'll mark this one as a feature request and we'll add the option later.