jt12
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jotego
FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
The ladder effect currently does not seem to exist within jt12 (unless I'm missing something and it's called something else). I was able to restore the functionality with what I...
There should be an overflow test [here](https://github.com/jotego/jt12/blob/master/hdl/mixer/jt12_fm_uprate.v#L49). Thanks to @greyrogue for pointing it out.
I used this core in 6-channel mode (by setting .num_ch(6)), but I noticed that the sound of some channels was slightly different from the real chip. Upon further investigation, I...
I have a question about the HDL code on this line. https://github.com/jotego/jt12/blob/42b19189044e079a9d93a9d728f67e64fbd0326f/hdl/adpcm/jt10_adpcm_cnt.v#L74 This combinational logic looks asymmetric. Because.. ``` (en_ch[1] && cur_ch[4]) ← diff = 3 (en_ch[2] && cur_ch[5]) ←...
Hello. As a preamble, I'm a beginner in Verilog (and FPGAs in general) though I've worked plenty with physical YM2612/3438 chips in the past. So I have a surface familiarity...
