Iztok Jeras

I am currently studying the synthesis part (yosys, abc). Could you point me (so I can look at the documentation/code) to where synthesis is telling the router (or Gate Resizer,...

For future reference, I found a few articles which seems to cover this under the name "Permutation Channel Routing Problem": - https://www.researchgate.net/publication/302334533_Permutation_Channel_Routing - https://dl.acm.org/doi/10.5555/1711932.1711942 - https://onlinelibrary.wiley.com/doi/10.1155/1994/68279 The following video mentions...

I noticed, the above code by itself does not cause a crash, instead it reports `Assignment pattern with too many elements`. I used the array in a `foreach` loop, so...

I got a small reproducible example. This is the SystemVerilog code: ```SystemVerilog module crash (); localparam logic [4-1:0] max_lst [5] = '{0, 1, 2**4-1}; endmodule: crash ``` And this is...

Sorry, I have no experience debugging C++. I do wish to learn and I do have some free time now, but I do not wish to commit to it. While...

This seems an impractical requirement in the standard. The most common use case, where you would be in violation of the rule is having a 32-bit system bus and 64-bit...

After I modified the offending line to: ``` fs_tx = $ungetc(32'(c_rx), fp_rx); ``` I got the next error: ``` $ make TOP=uart_model_tb verilator --binary -O3 -j 0 --timescale 1ps/1ps --x-assign...

I noticed the tests already cover the "optional assignment suppression character *", so I did not add any. I have run the code on EDAplayground https://www.edaplayground.com/x/CxuA Simulators VCS, Questa, Rivera...

Might be related to #2618

In a documentation generator, hashes would not be the best option, they are not really intended to be human readable. What I would like to see is an ordered list...