swapforth
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jamesbowman
Swapforth is a cross-platform ANS Forth
I'm trying to wrap my head around how the J1 core evolved over time and what version of the core are featured in which repositories/folders. My current understanding is that...
When I try to compile J1B (via `make` in `j1b/swapforth/j1b/verilator`), I get the old error: ``` verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-module j1b --exe sim_main.cpp %Error:...
Hi David ...... if you are listening these days ... :) I have completed the above port which includes a USB UART implemented in verilog. Works very well as a...
Hi there, I've tried building from scratch as per the reference document here: https://github.com/jamesbowman/swapforth/raw/master/j1a/doc/j1a-reference.pdf The Verilog seems to build and program OK, but when trying to connect using the python...
First thank you for this Python emulator. A great way for a Python developer to learn about the J1 CPU. So I fired it up. ` python3 nuc.py nuc.py:765: DeprecationWarning:...
Compilation of J1B with Verilator does not work in Linux/Debian. Small modification of j1b.v needed.
When I try to run the `j1b` emulated with Verilator in the `j1b/verilator` directory, I get the following error: verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-module j1b...
Forth allows certain base-setting prefixes in literals: e.g.,: * & – decimal * \# – decimal * % – binary * $ – hexadecimal unfortunately, it seems that in swapforth...
Hi James, Just letting you know I have an initial port of j1b to the ESP5 fpga. I intend to target the tinyFPGA-EX board once it get's released .. I...
fixes error when doing "#include swapforth.fs" according to the J1a SwapForth Reference guide: ``` u': create' u' :' u' here >body postpone literal' u' postpone ;' u';' u'' u'include core.fs'...
