MinecraftHDL
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itsFrank
A Verilog synthesis flow for Minecraft redstone circuits
https://user-images.githubusercontent.com/80766200/223428201-4cd080b5-9ca5-461f-a9d4-8875a277d977.mp4 nothing found in logs, verilog used: ```SystemVerilog module or_not_halfadder ( input Bit_1, input Bit_2, output Carry_out, output Sum ); assign Carry_out = ~ (~ Bit_1 | ~ Bit_2); assign...
after much debugging, and porting the code so it spits out a schematic instead of taking 8 hours to place moderately complex circuits in a world in a world, i...
In general, when the code tries to connect two tracks, the channel will be at least 3 blocks wide, and a repeater will be placed in the middle to extend...
Just an idea to use ProjectRed logic gates and multi colored wires / buses.
``` [01:03:47] [Server thread/INFO] [STDERR]: [minecrafthdl.block.blocks.Synthesizer:synth_gen:129]: minecrafthdl.MHDLException: Unknown Cell:ManuallyAdd [01:03:47] [Server thread/INFO] [STDERR]: [minecrafthdl.block.blocks.Synthesizer:synth_gen:129]: at GraphBuilder.GraphBuilder.resolveType(GraphBuilder.java:762) [01:03:47] [Server thread/INFO] [STDERR]: [minecrafthdl.block.blocks.Synthesizer:synth_gen:129]: at GraphBuilder.GraphBuilder.buildGraph(GraphBuilder.java:132) [01:03:47] [Server thread/INFO] [STDERR]: [minecrafthdl.block.blocks.Synthesizer:synth_gen:129]: at minecrafthdl.block.blocks.Synthesizer.synth_gen(Synthesizer.java:119)...
https://minecraft.curseforge.com/projects/super-circuit-maker Please add support for this mod because it will make designing circuits much easier
Can you add the Gradle files to the repository? I expect that you already have them in your working copy, and that they just got picked up by .gitignore. -...
I mentioned this on Reddit and I know it is a relatively big feet that would require some reorganizing, but I wanted to create an issue so if anyone was...
Since you have a page explaining how to contribute to this mod, I assume that contributions are welcome. Can you add a license to the code that makes this explicit?