rohd-cosim
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intel
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
### Motivation `Cosim` modules currently have the ability to specify things like simulation and compile time arguments. Sometimes, it might be useful to provide compile, simulation, or other arguments at...
There is a block of code in rohd_connector.py which is designed to detect whether there was a timeout waiting for the SystemVerilog simulator to complete a tick: ```python if not...
There may be scenarios where a user of the RohdConnector would want to know whether it had previously encountered some error in post-simulation routines. An indication other than an exception...
A `#` delay in the SystemVerilog simulator can result in signals changing at intermediate times between ticks and not edge triggered by any signal driven by ROHD Cosim. We should...
The `throwOnUnexpectedEnd` scenarios are under-tested for `PortConfig`.
We have existing tests with `PortConfig` for scenarios where errors occur during the simulation, but we should make sure simulations gracefully end even if the crash occurs before `Simulator.run` is...
The ROHD bug https://github.com/intel/rohd/issues/253 is preventing us from doing an `await` on `Simulator.reset()` in finish_test.dart because the simulation doesn't get marked as ended, which the reset will wait for. Once...
Testing for 0-width ports it blocked pending https://github.com/intel/rohd/issues/57. Some code for testing it is already started in cosim_test.dart.
There are some scenarios where ROHD Cosim will send multiple ticks to the SV simulator back-to-back without any additional value added (e.g. I think if there are no events in...
There can be situations where the SystemVerilog simulator needs to tick multiple times within one timestamp of the ROHD simulator. This scenario probably already happens, but it would be good...