[HIP] Compiling code for different AMD architectures

[densamoilov]

DPC++ with HIP AMD backend requires to specify a target architecture via -Xsycl-target-backend --offload-arch=gfx90a. This means that the code should be compiled for each architecture which may be a problem for libraries that have such code.

Is it possible to add support for AMD backend similar to CUDA via -fsycl-targets=nvptx64-nvidia-cuda?

[keryell]

Would it be possible to have just all the AMD GPU targets in -fsycl-targets too, since there is no PTX or SPIR-V before targeting the final ISA?

[densamoilov]

@keryell, is it a question to me?

[keryell]

Yes, I am considering alternatives too.

[densamoilov]

Can you please elaborate on what before targeting the final ISA means and your idea?

[keryell]

I think we agree on the feature. If the AMD workflow targets directly the ISA of the various AMD GPU architectures involved without any future JITing, why not considering them directly in -fsycl-targets as you propose, like -fsycl-targets=gfx90a-amd-hip or whatever?

[densamoilov]

I see, that makes sense. Specifying all architectures via -fsycl-targets would allow the performance libraries to avoid compiling them for a particular AMD architecture.

Is it feasible?

[ph0b]

any update on this issue ? This is important for applications targeting AMD GPUs in general.