[SYCL][Doc] Update SYCL_INTEL_data_flow_pipes extension for FPGA host pipe support

[pcolberg]

Add a memory order parameter to device-side read/write members and default to sycl::memory_order::seq_cst.

Replace min_capacity property with compile-time properties list for use with SYCL_INTEL_FPGA_data_flow_pipes_properties extension.

Add host pipe read/write members with additional sycl::queue parameter.

Cc: @mkinsner @GarveyJoe @aditikum @rho180 @zibaiwan