MemTestHelper

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tWR and tRTP does not provide much of performance uplift so we could have ignored them and left them to the end, but!! lower tRTP could mean lower tRAS and...

integralfx

IMC load

2

Which memory timings do you think that they mostly increase the load on the CPU IMC?

IslamGhunym

Minor notes to add for RTL and newer Intel generations

1

If user has tightened their RTL/IOLs, at times (especially after a bad crash or a power outage), the motherboard can simply fail to POST. If this happens, reset the RTL/IOLs...

nitorita

add StresKit to the testing software section

2

https://github.com/valleyofdoom/StresKit

BoringBoredom

Unclear wording regarding testing OCCT VRAM (what?)

2

`For AMD, run Prime95 Large FFTs and OCCT VRAM with max utilization simultaneously to stress the FCLK and ensure FCLK stability. This should be run after any frequency/FCLK change.` This...

Motophan

Remove P/S/T timing explanation

2

Every timing group affects everything, it does not make much sense to say that primary/secondary/third timings affect latency/bandwidth specifically.

HarrySIsNotAvailable

There is no underscore for other mentions of tWTRS/L. Had trouble finding this with ctrl + f.

HarrySIsNotAvailable

My aim in this PR is to change the order of tightening specific timings that depend on others first. 1. Moved tuning tCWL before tWTRS/L (which involves changing tWRRD) because...

HarrySIsNotAvailable

tCL tCWL dependency

5

Currently, tCWL depends on tCL as the following is stated: | Timing | Safe | Tight | Extreme | | :----: | :--: | :---: | :-----: | | tCWL1...

ghost

> Removes 16-20-20-40 timing suggestion for

integralfx