Processor-UVM-Verification
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gupta409
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
Hi gupta409, I run your code with vcs simulator but get scoreboard issue about LOAD and MOVE command. >> UVM_ERROR processor_scoreboard.sv(264) @ 11030000: uvm_test_top.env.sb [LOAD_FAIL] Actual Calculation=16384 Expected Calculation= 0...
It would be nice to have a ready to run version of the project in EDA Playground. This would require loading the code and setting up the project in EDA...
Currently the project is in it's extremely vanilla form. There is a need for details to be listed in the Readme.md. Most of the details can be found in the...