Lower function invocations to Verilog module instantiations

[meheff]

Discussed in https://github.com/google/xls/discussions/646

^{Originally posted by joachimschmidt557 June 27, 2022} Hi! I was wondering whether it would be possible to lower DSLX function invocations to module instantiations in the codegen pass. A small example:

fn foo(a: u32, b:u32) -> u32 {
  a + b
}

fn test(a: u32, b:u32) -> u32 {
  foo(a, b)
}

Converted to XLS IR, this produces

package test

fn __test__foo(a: bits[32], b: bits[32]) -> bits[32] {
  ret add.3: bits[32] = add(a, b, id=3, pos=0,1,4)
}

fn __test__test(a: bits[32], b: bits[32]) -> bits[32] {
  ret invoke.6: bits[32] = invoke(a, b, to_apply=__test__foo, id=6, pos=0,5,5)
}

Currently, when the invoke IR instruction is encountered by codegen_main, an error message is emitted. Would it be possible to convert that invoke instruction into a Verilog module instantiation and thus "preserve the function/module hierarchy"? Like this:

module __test__foo(
  input wire [31:0] a,
  input wire [31:0] b,
  output wire [31:0] out
);
  assign out = a + b;
endmodule

module __test__test(
  input wire [31:0] a,
  input wire [31:0] b,
  output wire [31:0] out
);
  foo foo_0(a, b, out);
endmodule