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Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.git...

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(CFU Playground) Automated sync from github.com/tensorflow/tflite-micro

Hi @tcal-x , I've tried to profile some cfu-function calls for my accel. design and as well as for a "test-setup". I'm seeing some unusually high cycle times. For ex:-...

Hi! I'm hoping to test out running classification on some of my own images using the CFU-Playground framework with the mnv2 model. I wanted to ask exactly what kind of...

After the recent dependency bump (#619), I thought that it caused the KWS project to no longer fit on Fomu (over the limit by ~80 LCs). But then I was...

Use Conda if you need Yosys. Signed-off-by: Tim Callahan

Hi @tcal-x , I had a general doubt regarding synthesis of the Vexriscv core with the accelerator peripheral designed on an fpga. Are the memory resources used in synthesis restricted...

Hello, If this is error has been observed before, can someone please point me in the right direction ? Thanks Raj make[4]: Entering directory '/home/rajsaktish/repos/all_CFU_space/synth_BG/CFU-FLOW/soc/build/digilent_arty.mnv2/gateware' symbiflow_synth -t digilent_arty -v /home/rajsaktish/repos/all_CFU_space/synth_BG/CFU-FLOW/proj/mnv2/cfu.v...

I've been playing around with CFU playground and want to test my custom model. It would be great if the steps for adding one's own model gets documented.

This introduces PLL into HPS design with an additional option to enable/disable output clocks. It makes power consumption much higher. Initial tests with multimeter result in 70mW when CFU is...

When bumping VexRiscv and pre-generated verilog to recent master, we saw hangs using the CFU using either locally generated verilog files, or those generated upstream. Original discussion here: https://github.com/google/CFU-Playground/pull/592#issuecomment-1136534363. @davidlattimore...