Giacomo Travaglini
Giacomo Travaglini
> @giactra, could you review this PR? You reviewed a couple of others, and this one might have slipped through. Thanks. Hi Ivana, I didn't comment but I actually did...
Hi all, apologies for my late reply. I will try to come up with some examples/information sometime next week
Apologies, it took me some time to extract some data. Basically this PR is breaking the decoding of some VCMLAs. For example 0xfe2f78ae would not be recognised as a valid...
This PR does not detail much on what it is trying to do, but anyway I feel you should keep an eye on https://github.com/gem5/gem5/pull/1446 as there might be some overlap
> > Is there a reason for having a PciToPciDevice as a separate SimObject? Are we expecting users to provide a different one? > > As PciBridge inherits from PciDevice,...
@clemdiep What's the status of this PR? Does it need rebasing? Is it ready for a new round of review?
Hi @Joao-Pedro-Cabral, this PR should be tagged as "cpu-o3" as it is effectively touching cpu-o3 code. I have no familiarity with the riscv ISA, but from a quick look at...
> Hello @giactra , I changed the PR name. In this case, `vsetvl` isn't the producer of `vnsrl` source registers, but the problem here isn't correlated only to `vnsrl` instruction,...
Thanks @cosmiclat05 for this contribution! I know this has been pushed in draft mode so I will hold most of my comments for the time being until you mark this...
Hi @cosmiclat05, next week I will spend some time providing a proper review to the entire PR. In the meantime, can I ask you to rebase your PR to fix...